Edge-controlled flip flops or edge-controlled master/slave latch pairs are essential basic building blocks for synchronizing multi-stage logic circuits. They are used in almost all modem integrated digital circuits such as digital signal processors (DSPs), microprocessors and integrated circuits for communication applications for increasing the data flow by means of pipelining. For applications with low active power dissipation, flip flops and master/slave latch pairs must still operate reliably and have sufficient switching speed when the difference between a supply voltage VDD and a threshold voltage of the transistors VT is low, that is to say when the gate overdrive voltage VDD-VT is low.
In an implementation with modem sub-100 nm or CMOS technologies, it is apparent, however, that the parasitic capacitances of the MOS transistors form a part of the total capacitance to be driven which is not negligible. It is especially the junction and gate overlap capacitances between drain terminal and an internal or external output node which slow down the switching process. Particular attention must be paid to the fact that the gate-drain capacitances appear to be twice as large due to the Miller effect since both the gate potentials and the drain potentials change oppositely on a timescale of approximately 10 ps to 30 ps in the dynamic range.
In contrast to other circuit arrangements such as edge-controlled master/slave latch pairs, edge-controlled flip flops based on sense amplifiers have a high switching speed even with a low gate overdrive VDD-VT, see Marcovic, D., Nikolic, B., Brodersen, R. W. “Analysis and Design of Low-Energy Flip-Flops”, Proc. of the International Symposium on Low Power Electronics and Design (ISLPED) 2001, Huntington Beach, USA, pp. 52-55.
With regard to robustness, flip flops based on sense amplifiers are less sensitive to process variations at low supply voltages than master/slave latch pairs as is disclosed in Dao, H. Q., Nowka, K., Oklobzija, V. G. “Analysis of Clocked Timing Elements for Dynamic Voltage Scaling Effects over Process Parameter Variation”, Proc. of the International Symposium on Low Power Electronics and Design (ISLPED) 2001, Huntington Beach, USA, pp. 56-59.
After the introduction of such flip flops (see U.S. Pat. No. 6,232,810), improvements were made. Thus, for example, it was possible to achieve a more symmetric switching behavior, that is to say identical clock signal/flip flop signal delay times (CLK-Q delay times, with clock signal CLK, flip flop signal Q, inverted flip flop signal/Q) for a flip flop with the differential outputs Q and /Q.
In the further text, a circuit arrangement 100 as disclosed in U.S. Pat. No. 6,232,810 is described with reference to FIG. 1.
The circuit arrangement 100 is formed from a pulse generator part-circuit 101, a flip flop part-circuit 102 and a switching part-circuit 103.
In the pulse generator part-circuit 101, a clock signal CLK is provided at a clock signal input 104. The clock signal input 104 is coupled to the gate terminal of an n-MOS clock pulse field effect transistor 105. A first source/drain terminal of the n-MOS clock pulse field effect transistor 105 is connected to the electrical ground potential VSS 115. A second source/drain terminal of the n-MOS clock pulse field effect transistor 105 is coupled to a first source/drain terminal of a first n-MOS logic field effect transistor 106, at the gate terminal of which a data signal D is applied. The second source/drain terminal of the n-MOS clock pulse field effect transistor 105 is also coupled to a first source/drain terminal of a second n-MOS logic field effect transistor 107, at the gate terminal of which a data signal /D is applied which is complementary to the data signal D. A second source/drain terminal of the first n-MOS logic field effect transistor 106 is coupled to a first source/drain terminal of an n-MOS bypass field effect transistor 108, the gate terminal of which is connected to an electrical potential VDD. A second source/drain terminal of the n-MOS bypass field effect transistor 108 is coupled to a second source/drain terminal of the second n-MOS logic field effect transistor 107. Furthermore, a second source/drain terminal of the first n-MOS logic field effect transistor 106 is coupled to a first source/drain terminal of a first n-MOS signal transfer field effect transistor 109. A second source/drain terminal of the first n-MOS signal transfer field effect transistor 109 is coupled to a first source/drain terminal of a first p-MOS clock pulse field effect transistor 111 and to a first source/drain terminal of a first p-MOS feedback field effect transistor 112. A second source/drain terminal of the first p-MOS clock pulse field effect transistor 111 and a second source/drain terminal of the first p-MOS feedback field effect transistor 112 are connected to the electrical potential of the supply voltage VDD 116. Furthermore, the gate terminal of the first n-MOS signal transfer field effect transistor 109 is coupled to the gate terminal of the first p-MOS feedback field effect transistor 112. The second source/drain terminal of the second n-MOS logic field effect transistor 107 is coupled to a first source/drain terminal of a second n-MOS signal transfer field effect transistor 110, the second source/drain terminal of which is coupled to a first source/drain terminal of a second p-MOS clock pulse field effect transistor 113 and to a first source/drain terminal of a second p-MOS feedback field effect transistor 114. The gate terminal of the second n-MOS signal transfer field effect transistor 110 is coupled to the gate terminal of the second p-MOS feedback field effect transistor 114. Furthermore, a second source/drain terminal of the second p-MOS clock pulse field effect transistor 113 and a second source/drain terminal of the second p-MOS feedback field effect transistor 114 are connected to the electrical potential of the supply voltage VDD 116. The gate terminal of the first p-MOS clock pulse field effect transistor 111 is coupled to the clock signal input 104. Furthermore, the clock signal input 104 is coupled to the gate terminal of the second p-MOS clock pulse field effect transistor 113.
In the further text, the interconnection within the flip flop part-circuit 102 is described.
A first source/drain terminal of a first p-MOS flip flop field effect transistor 125 is connected to the supply potential VDD 116. Furthermore, a second source/drain terminal of the first p-MOS flip flop field effect transistor 125 is coupled to a first source/drain terminal of a first n-MOS flip flop field effect transistor 126, the second source/drain terminal of which is connected to the electrical ground potential 115. A first source/drain terminal of a second p-MOS flip flop field effect transistor 127 is connected to the electrical ground potential 115. A second source/drain terminal of the second p-MOS flip flop field effect transistor 127 is coupled to a first source/drain terminal of a second n-MOS flip flop field effect transistor 128, the second source/drain terminal of which is connected to the electrical ground potential 115. The gate terminal of the first p-MOS flip flop field effect transistor 125 and the gate terminal of the first n-MOS flip flop field effect transistor 126 are coupled to one another and form a storage node /Q of the flip flop part-circuit 102. Furthermore, the gate terminal of the second p-MOS flip flop field effect transistor 127 and the gate terminal of the second n-MOS flip flop field effect transistor 128 are coupled to one another and form a storage node Q of the flip flop part-circuit 102. The second source/drain terminal of the first p-MOS flip flop field effect transistor 125 is coupled to the gate terminal of the second p-MOS flip flop field effect transistor 127. Furthermore, a second source/drain terminal of the second p-MOS flip flop field effect transistor 127 is coupled to the gate terminal of the first n-MOS flip flop field effect transistor 126.
In the further text, the interconnection within the switching part-circuit 103 is described.
A first source/drain terminal of a first p-MOS switching field effect transistor 117 is connected to the supply potential 116. A second source/drain terminal of the first p-MOS switching field effect transistor 117 is coupled to a first source/drain terminal of a first n-MOS switching field effect transistor 118, the second source/drain terminal of which is connected to the electrical ground potential 115. Furthermore, a first source/drain terminal of a second p-MOS switching field effect transistor 119 is connected to the electrical supply potential 116. A second source/drain terminal of the second p-MOS switching field effect transistor 119 is coupled to a first source/drain terminal of a second n-MOS switching field effect transistor 120, the second source/drain terminal of which is connected to the electrical ground potential 115.
A first source/drain terminal of a third p-MOS switching field effect transistor 121 is connected to the electrical supply potential 116. A second source/drain terminal of the third p-MOS switching field effect transistor 121 is coupled to a first source/drain terminal of a third n-MOS switching field effect transistor 122, the second source/drain terminal of which is connected to the electrical ground potential 115. The gate terminal of the third p-MOS switching field effect transistor 121, the gate terminal of the third p-MOS switching field effect transistor 122 and the gate terminal of the second p-MOS switching field effect transistor 119 are coupled to one another. Furthermore, a first source/drain terminal of a fourth p-MOS switching field effect transistor 123 is connected to the supply potential 116. A second source/drain terminal of the fourth p-MOS switching field effect transistor 123 is coupled to a first source/drain terminal of a fourth n-MOS switching field effect transistor 124, the second source/drain terminal of which is connected to the electrical ground potential 115. The gate terminal of the fourth p-MOS switching field effect transistor 123, the gate terminal of the fourth n-MOS switching field effect transistor 124 and the gate terminal of the first p-MOS switching field effect transistor 117 are coupled to one another.
In the further text, the interconnection of the part-circuits 101, 102, 103 with one another is described.
The gate terminal of the second p-MOS feedback field effect transistor 114 is coupled to the gate terminal of the first p-MOS switching field effect transistor 117. Furthermore, the gate terminal of the first p-MOS feedback field effect transistor 112 is coupled to the gate terminal of the second p-MOS switching field effect transistor 119. The second source/drain terminal of the third p-MOS switching field effect transistor 121 is coupled to the gate terminal of the first n-MOS switching field effect transistor 118. The second source/drain terminal of the fourth p-MOS switching field effect transistor 123 is coupled to the gate terminal of the second n-MOS switching field effect transistor 120. The second source/drain terminal of the first p-MOS switching field effect transistor 117 is coupled to the gate terminal of the second p-MOS flip flop field effect transistor 127. Furthermore, the second source/drain terminal of the second p-MOS switching field effect transistor 119 is coupled to the second source/drain terminal of the second p-MOS flip flop field effect transistor 127.
At the gate terminal of the second p-MOS feedback field effect transistor 114, an input signal /S generated by the pulse generator part-circuit 101 is provided for the flip flop part-circuit 102. Furthermore, an input signal /R of the flip flop part-circuit 102, generated by the pulse generator part-circuit 101, is provided at the gate terminal of the first p-MOS feedback field effect transistor 112.
In the further text, the operation of the circuit arrangement 100, which represents an edge-controlled flip flop based on sense amplifiers, is described.
With regard to the basic circuit building blocks, the edge-controlled flip flop in FIG. 1 is a circuit arrangement 100 which has the pulse generator circuit 101 formed from the transistors 105 to 114. Depending on the signals at the data inputs D and /D on the rising edge of the clock signal CLK, the internal inputs S, /S, R, /R of a set/reset flip flop (formed from the transistors of the flip flop part-circuit 102 and the switching part-circuit 103) are set. The output signals /S and /R of the pulse generator part-circuit 101 are precharged to the electrical supply potential VDD 116 via the p-MOS transistors 111, 113 during a precharging phase (i.e. CLK at a logical value “0”). When data signals D and /D are present, either the channel region of the first n-MOS logic field effect transistor 106 or that of the second n-MOS logic field effect transistor 107 conduct so that either /S or /R is pulled down to the electrical potential VSS 115 directly after the rising clock edge of CLK (i.e. out of the transition of CLK from a logic value “0” to a logic value “1”).
This functionality is based on the disclosure of U.S. Pat. No. 4,910,713 with respect to differential flip flops via a differential sense amplifier.
The n-MOS bypass field effect transistor 108 has minimum dimensions and, following the rising clock edge, generates electrical coupling from a source/drain terminal of the first n-MOS signal transfer field effect transistor 109 and from a source/drain terminal of the second n-MOS signal transfer field effect transistor 110 to the electrical ground potential VSS 115 and ensures static operation. In this manner, the state of the pulse generator part-circuit 101 is stable after the rising clock edge.
The set/reset output stage from FIG. 1 is disclosed in U.S. Pat. No. 6,232,810.
Another circuit arrangement is described in U.S. Pat. No. 6,107,853.
Other flip flop circuits comprising a clock pulse field effect transistor and a logic field effect transistor are described in JP 200299623 A and U.S. Pat. No. 6,448,829 B1.
In summary, the circuit arrangements with pulse generator circuits, known from the prior art, are not sufficiently fast with respect to the switching speed for many applications.